Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!think.com!linus!alliant!neray
From: neray@Alliant.COM (Phil Neray)
Newsgroups: comp.arch
Subject: Re: RISC vs. CISC -- SPECmarks
Message-ID: <4668@alliant.Alliant.COM>
Date: 13 May 91 19:46:09 GMT
References: <1991May2.162909.9165@news.arc.nasa.gov> <819@cadlab.sublink.ORG> <1991May7.061500.7485@marlin.jcu.edu.au>
Organization: Alliant Computer Systems Corp.
Lines: 44

1. Yes, superscalar RISC is essentially SISD (even when it has pipelining
like the i860), but you're missing the point - the real leap forward is
putting lots of these RISC/superscalar/pipelined microprocessors in a
a large parallel system with either shared memory (eg., Alliant FX/800 and
FX/2800)) or distributed memory (eg., Intel iPSC/860), and then you're
talking about MIMD. Since the i860 has 1 million transistors on a single
chip, we can put four processors on a single 12"x13" processor module.

MIMD architectures like these handle all of the vector-style algorithms PLUS 
the ones that are not suited to hardware vector architectures (such as loops 
with dependencies, or loops with subroutines).

And, you can still implement vector-style algorithms at the individual
processor level by using pipelining to keep the pipelines full, using the 
cache as "vector registers". In addition, superscalar architectures promote 
optimal pipelined performance by allowing load instructions to be issued 
simultaneously with floating-point instructions.

For example, an FX/2800 with 28 i860-based processors achieves 1018 MFLOPS
on a complex double-precision BLAS3 matrix multiply, and over 2 GFLOPS on 
single-precision convolutions.

2. "RISC + vectors"?

Ardent tried this in their first-generation system with limited success.

The new Convex systems are claimed to be RISC, but this is clearly a
spin-doctor, PR strategy to deal with a creeping realization by Convex 
that parallel RISC is becoming invevitable. The new systems are binary
compatible with the current C2 Series and the first-generation C1 that
was designed in the early 80s. This 128-element vector CISC architecture is 
clearly not RISC (it doesn't have a simple instruction set, and the 
instructions do not execute typically in a single clock cycle - a 128-
element vector instruction will require over 128 clock cycles). 

Convex is claiming that the new systems are RISC because they use fewer 
VLSI chips than their predecessors ... and the WSJ cheerfully quoted
"RISC" as meaning "Reduced Instruction Set Chips" ... oh well, maybe
the "Post" got it right.
-- 
Phil Neray			Domain:	neray@alliant.com
Alliant Computer Systems	UUCP:	{mit-eddie|linus}!alliant!neray
Littleton, MA 01460		Phone:	(508) 486-1429