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From: holmer@ucbarpa.Berkeley.EDU (Bruce K. Holmer)
Newsgroups: comp.arch
Subject: Control hardware for pipelined RISC processors (question)
Message-ID: <42136@ucbvax.BERKELEY.EDU>
Date: 14 May 91 00:52:51 GMT
Sender: nobody@ucbvax.BERKELEY.EDU
Reply-To: holmer@ucbarpa.Berkeley.EDU (Bruce K. Holmer)
Organization: University of California, Berkeley
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[]

I would like any information or references to articles/books
concerning the control part of pipelined RISC processors.  Kogge (The
Architecture of Pipeline Computers, McGraw-Hill 1981) distinguishes
two basic types of pipeline control: data stationary and time
stationary.  He also mentions another variant, modified data
stationary.

What I would like is a detailed description of the control hardware
used in current commercial RISC processors.  Block diagrams are
helpful, but I would really like to know things like:

Is the opcode decoded once-and-for-all immediately after it is fetched
and the control signals delayed the necessary amount (depending on
which stage of the pipe the control signal goes to)?  [this is Kogge's
modified data stationary control]

Does the opcode pass down its own pipeline and get decoded at each
stage of the pipeline (with the possibility of the opcode being
modified somewhere down the pipe)?  [this is Kogge's data stationary
control]

There are many other possible variations.


Thanks in advance,
Bruce Holmer
holmer@ucbarpa.berkeley.edu