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From: marshall@manse.cs.man.ac.uk (Robert Marshall)
Newsgroups: comp.lang.vhdl
Subject: Naive question(?) about component configurations
Keywords: component configuations
Message-ID: <1991May9.115451.1@manse.cs.man.ac.uk>
Date: 9 May 91 11:54:51 GMT
Sender: news@cs.man.ac.uk
Reply-To: rmarshall@cs.man.ac.uk
Organization: Department of Computer Science, University of Manchester
Lines: 38

Can anyone tell me of the rationale behind the `component_configuration's being
in the declarative part of the architecture?

What is the statement declaring, the instantiation label? To my way of thinking
the configuration is providing associations between previously declared
`entities'(not the VHDL keyword!) that will be resolved at elaboration time
rather than a declaration.
The motivation behind the question is:
does the configuration apply to the component or to the instantiations?
Yes I know it applies to both! but in your conceptual model of the design is
the following:
component x port(...) end component;
for all : x use entity a;
...
x1 : x...;
x2 : x...;
x3 : x...;
x4 : x...;

just a shorthand for:
----

for x1 : x use entity a;
for x2 : x use entity a;
for x3 : x use entity a;
for x4 : x use entity a;
 or is it saying something about the `virtual design unit' declared by the
component? In other words does the component configuration logically belong to
the component declaration or the individual instantiations?

Robert
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Robert A.J.Marshall,		EMAIL: rmarshall@cs.man.ac.uk
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