Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sun-barr!newstop!sun!amdcad!dvorak.amd.com!proton!tim From: tim@proton.amd.com (Tim Olson) Newsgroups: comp.sys.amiga.advocacy Subject: Re: 8-bit death Message-ID: <1991May12.204607.22101@dvorak.amd.com> Date: 12 May 91 20:46:07 GMT References: <3515.tnews@templar.actrix.gen.nz> <1991May10.183627.29486@neon.Stanford.EDU> <3626.tnews@templar.actrix.gen.nz> Sender: usenet@dvorak.amd.com (Usenet News) Reply-To: tim@amd.com (Tim Olson) Organization: Advanced Micro Devices, Austin, TX Lines: 38 In article <3626.tnews@templar.actrix.gen.nz> jbickers@templar.actrix.gen.nz (John Bickers) writes: | Quoted from <1991May10.183627.29486@neon.Stanford.EDU> by torrie@cs.stanford.edu (Evan Torrie): | > My recollection of PDP-11 V7 Unix was that all system calls were invoked | > via a trap instruction, with a word afterwords encoding which call was | | Perhaps that was the best way to do it on a PDP-11. What are some of | the same folks doing now with Plan-9 on modern hardware? The same thing. | What other considerations are there? I looked up the assembler for | the PDP-11, and it appears a TRAP is a bit slower than a JSR. Is | there something to do with the state of the machine that is useful | to OS functions when a TRAP is used instead of a JSR (for a PDP-11, | or for a 680x0?)? UNIX processes operate in two modes: user and kernel. When operating in user mode, the processes are prevented from performing certain CPU instructions which could crash the system. To switch to kernel mode, the CPU state must change from user to supervisor (to allow execution of priveledged instructions). a "JSR" instruction will not do this. Instead, some type of TRAP instruction is usually executed to affect this change. | In any case, I'm surprised. Is the Amiga OS the only rational one | in this bunch, eh? Are you sure that system calls to Amiga OS *don't* use some sort of TRAP instruction (usually hidden in a library routine). I seem to remember discussions of user-code trying to access the SR and failing on the 68010, which protects that register in user-mode. If so, then the code must be running in user-mode, and it must somehow switch to supervisor-mode at some point... -- -- Tim Olson Advanced Micro Devices (tim@amd.com)