Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!sdd.hp.com!hp-pcd!hpfcso!hpfcdc!chuckc
From: chuckc@hpfcdc.HP.COM (Chuck Cairns)
Newsgroups: comp.sys.hp
Subject: Re: A benchmark
Message-ID: <5570629@hpfcdc.HP.COM>
Date: 9 May 91 05:55:09 GMT
References: <1991May3.023705.5616@marlin.jcu.edu.au>
Organization: HP Fort Collins, Co.
Lines: 35

Hi,  
Curious HP type here.
Just wondered what your memory access pattern is on this particular 
benchmark. If you access memory address X then X+1 do you take a large hop
in memory location?  What I'm suspecting is that your benchmark may be
cache-thrashing. I.E. causing lots of accesses to main-ram. I'd
like to see the actual numbers on the higher speed IBM's. I kinda suspect
that they wouldn't scale well with clock speed. Hmmm  What't the cache to
main-ram width on the IBM's.

Why?
If we assume a very fast floating point processor, which both the HP730 
and the high end IBM's have, then the job becomes one of feeding
the FP processor with enough data quickly enough. Since all the vendors
draw from roughly the same pool for memory components their speed becomes
at least one limiting factor. How wide the cache-to processor bus is or how
many bytes-are in a cache line may not be pertinent IF you're cache thrashing.
If we drop out of cache into main ram then we're going to take a major hit
even with an efficient main-ram to cache-ram to FP processor path. A wider
path cache to main-ram would help ... but costs $$. More cache helps ... 
until the arrays get bigger .. it costs $$. Faster memory chips help but
they cost $$  Murphy's Nth law of $$? I bet we could roughly predict the 
speed of a given program by knowing the cache to main-ram width and the speed
of main-ram memory ... IF we also know that said program IS cache thrashing.

Since I don't know your particular benchmark these may not be applicable
ideas ...  Is it possible to run the benchmark with "rows and columns" 
exchanged ? I'd also be keen on knowing what happens when the 730 runs
totally from it's 256Kbyte data cache i.e. ... smaller arrays.

The brakes on a Pinto at 55 may seem "spongy" on a Ferrari at 135 ?
The ram chips on an XYZ at 5 MFLOPS may seem ...

Regards, Chuck Cairns 
As usual: My opinions are my own and not HP's.