Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!sdd.hp.com!hp-pcd!hpfcso!cag
From: cag@hpfcso.FC.HP.COM (Craig Gleason)
Newsgroups: comp.sys.hp
Subject: Re: Upgrade or Snakes ?
Message-ID: <7370393@hpfcso.FC.HP.COM>
Date: 9 May 91 22:45:05 GMT
References: <1295@theseas.ntua.gr>
Organization: Hewlett-Packard, Fort Collins, CO, USA
Lines: 18

>  The Model 850S has a combined (I & D) 128KB cache, the Snakes have
>at LEAST double this, TLB is 4K on 850S, ? on Snakes (can't find,
>but page size in HP-PA has doubled from 2K to 4K and the TLB
>has some interesting optimization that allow mapping multiple
>contiguous virtual pages).  

The Snakes TLB's are split I/D, 96 entries (fully associative) each.
There are also "super-TLB" entries which can map up to 16MB of contiguous
memory each.  Several PA-RISC 1.1 features were added to cut the TLB
miss penalty and improve TLB performance in general (including the page
size change mentioned above).

Snakes caches are 128kB instruction, 256kB data for the 720/730 and
256kB I/256kB D for the 750.  These are direct mapped, as opposed to
the two-way associative caches on the 870 (I'm not sure exactly what
configuration the 865 is).

Craig Gleason