Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!sdd.hp.com!hp-pcd!hpsgwp!plim From: plim@hpsgwp.sgp.hp.com (Peter Lim) Newsgroups: comp.sys.ibm.pc.hardware Subject: Re: INFO ON NEW GATEWAY 2000 COMPUTERS?? Message-ID: <3370025@hpsgwp.sgp.hp.com> Date: 9 May 91 05:50:07 GMT References: <11889@uwm.edu> Organization: HP Singapore IC Design Ctr Lines: 29 / n65j@vax5.cit.cornell.edu / 8:07 am May 8, 1991 / writes: $ clock rate for the SX, even though they do for everything else. A cached $ 20 MHz SX might well outperform an uncached 20 MHz DX. The memory $ architecture and speed rating (which determine memory wait states) might $ also differ. $ How ? Assuming the 20 MHz SX is running at zero wait state and the 20 MHz DX is running at 1 wait state. Given that SX take 2 cycle to fetch 32 bit and DX does that in 1 cycle, this would mean the SX running at the same speed as a DX. Actually, cached machine doesn't give you exactly 0 wait state (just close to zero). And these days any 386 design would have some kind of interleave memory which usually reduce wait state to less than 1. These 2 points mean that 20 MHz DX should run faster than 20 MHz SX ---- unless you are not fetching 32 bit data. Regards, ___o``\________________________________________________ ___ __ _ _ Peter Lim. V````\ @ @ . .. ... .- -> 76 MIPS at under US$20K !! --- -- - - /.------------------------------------------------ === == = = >--_// . .. ... .- -> 57 MIPS at under US$12K !! `' . If you guessed SUN, IBM or DEC, you are wrong ! E-mail: plim@hpsgwg.HP.COM Snail-mail: Hewlett Packard Singapore, Tel: (065)-279-2289 (ICDS, ICS) Telnet: 520-2289 1150 Depot Road, Singapore 0410. #include