Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!apple!voder!pyramid!leadsv!practic!polstra!jdp From: jdp@polstra.UUCP (John Polstra) Newsgroups: comp.sys.mips Subject: Re: R2000/3000 Pipeline Questions Message-ID: <8363@polstra.UUCP> Date: 6 May 91 21:00:57 GMT References: <8179@polstra.UUCP> Organization: Polstra & Co., Inc., Seattle Lines: 31 In article ychen@sp1.csrd.uiuc.edu (Yung-Chin Chen) writes: >In article <8179@polstra.UUCP> jdp@polstra.UUCP (John Polstra) writes: > >> I notice in each case that the MIPS assembler does not insert a NOP >> after the first load instruction. Note: these examples will seem less >> stupid if you imagine that the first instruction is in the delay slot of >> a conditional branch. > > Don't reply on assembly code (compile with -S option). That is not >the real object code. The smart MIPS assembler will re-ordering these >codes to eliminate register interlock problems. Your question is only >one case of such problems. Only re-ordering failure ( instruction >shuffle will result in incorrect execution) will result an extra NOP >instruction. That is what I know and I hope it is right. > >ychen >---------------- >UIUC, CSRD Yes, I was aware that the MIPS assembler reorders instructions. I did examine the actual object code, using DBX. Keith Garrett of MIPS answered my questions with a very informative post. Briefly, when two consecutive instructions both modify the same register, the second instruction will always determine the final content of the register. -- John Polstra polstra!jdp@uunet.uu.net Polstra & Co., Inc. ...!uunet!polstra!jdp Seattle, Washington USA (206) 932-6482 "Self-knowledge is always bad news." -- John Barth