Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!think.com!spool.mu.edu!snorkelwacker.mit.edu!bloom-beacon!eru!hagbard!sunic!mcsun!ukc!acorn!armltd!abaum From: abaum (Allen Baum) Newsgroups: comp.arch Subject: Re: Compilers and efficiency Message-ID: <168@armltd.uucp> Date: 14 May 91 15:37:52 GMT Article-I.D.: armltd.168 References: <1991May13.211555.28824@rice.edu> Sender: abaum@armltd.uucp Distribution: comp Organization: A.R.M. Ltd, Swaffham Bulbeck, Cambs, UK Lines: 19 In article <1991May13.211555.28824@rice.edu> preston@ariel.rice.edu (Preston Briggs) writes: >It's easy to get old instructions (say int x int -> long int) in 1 cycle, >just slow the cycle time down to old rates. It's easy to do now, with the same cycle times. Cycle times are not the issue in this case. The issue is one of returning two results, and what to do with them. The are various solutions, almost all are disliked by either compiler writers, architects, or chip designers. These solutions include specifying two destination registers in the instruction, overwriting one or both of the source registers, writing back to dest reg/dest reg+1 pair, keeping the upper half in a special register..... you can probably think of more, and come up with the reasons that each of the groups above dislike it. The reasons for disliking them aren't terribly frivolous either- they just outweigh the advantages of returning both (in the eyes of those particular groups, AT the particular time - times change!)3