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From: edwardm@hpcuhe.cup.hp.com (Edward McClanahan)
Newsgroups: comp.arch
Subject: Re: Memory hierarchies
Message-ID: <32580032@hpcuhe.cup.hp.com>
Date: 13 May 91 22:44:51 GMT
References: <1991May7.152224.3146@rice.edu>
Organization: Hewlett Packard, Cupertino
Lines: 26

> %The reality of big systems is that they are implemented with a
> %memory hierarchy.  Typically
> %
> %	registers
> %	cache
> %	tlb
> %	ram
> %	disk

> Actually, *really* big systems look something like this:

> registers
> (cache)
> ram
> solid-state disk
> fast disk
> (slower disk)
> tape

Or, how about the following:

  registers
  register-window
  on-chip cache                 on-chip tlb
  off-chip cache                off-chip tlb
  ...