Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!samsung!uakari.primate.wisc.edu!news.larc.nasa.gov!grissom.larc.nasa.gov!kludge
From: kludge@grissom.larc.nasa.gov ( Scott Dorsey)
Newsgroups: comp.arch
Subject: Re: What's in the '586?
Message-ID: <1991May15.152351.11276@news.larc.nasa.gov>
Date: 15 May 91 15:23:51 GMT
References: <1991May14.002130.4740@vax5.cit.cornell.edu> <42347@cup.portal.com>
Sender: news@news.larc.nasa.gov (USENET Network News)
Reply-To: kludge@grissom.larc.nasa.gov ( Scott Dorsey)
Organization: NASA Langley Research Center
Lines: 15

In article <42347@cup.portal.com> mmm@cup.portal.com (Mark Robert Thorson) writes:
>Although from the programmer's point of view the software model of the 586
>is an upward-compatible superset of the 486, the underlying implementation
>is radically different, especially with regard to the cache.  While the
>486 has a unified instruction/data cache, the 586 has separate caches for
>the CS, SS, DS, ES, FS, and GS segments...

>A novel method has been developed for reducing the cost of floating-point
>performance to the end user.  Each 586 has 100 bytes of EPROM for
>storing passwords unique to each chip.  When a user decides to upgrade
>to hardware floating point, he simply calls Intel and buys the password
>for enabling the on-chip FPU...

This is a joke, right?  Please tell me that this is a joke.
--scott