Path: utzoo!utgpu!news-server.csri.toronto.edu!bonnie.concordia.ca!uunet!kithrup!sef
From: sef@kithrup.COM (Sean Eric Fagan)
Newsgroups: comp.arch
Subject: Re: VISC - A way to speed up moto cisc mpu's?
Message-ID: <1991May15.183328.22820@kithrup.COM>
Date: 15 May 91 18:33:28 GMT
References: <1991May15.110000.25800@Daisy.EE.UND.AC.ZA>
Organization: Kithrup Enterprises, Ltd.
Lines: 17

In article <1991May15.110000.25800@Daisy.EE.UND.AC.ZA> mcdonald@Daisy.EE.UND.AC.ZA (Bruce J McDonald) writes:
>Variant Instruction Set Computers - VISC
>
>ALU width all 64 bits.  Introduce an exclusive mode switch instruction
>which would switch in an enhanced, RISC-like micro-engine, with totally
>new instruction set geared for 64bit operations.

Uhm, it would probably be better to devote all that chip space to the "RISC"
processor and ship a software emulator.  If one puts in enough cache on the
chip, one might even be able to make the entire emulator fit in cache (see
Henry Spencer).

-- 
Sean Eric Fagan  | "I made the universe, but please don't blame me for it;
sef@kithrup.COM  |  I had a bellyache at the time."
-----------------+           -- The Turtle (Stephen King, _It_)
Any opinions expressed are my own, and generally unpopular with others.