Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!think.com!mintaka!ai-lab!raisin-scone!lethin From: lethin@raisin-scone.ai.mit.edu (Richard A. Lethin) Newsgroups: comp.arch Subject: Re: Memory speed, why so slow? Message-ID: <15962@life.ai.mit.edu> Date: 16 May 91 18:43:31 GMT References: <9245@idunno.Princeton.EDU> Sender: news@ai.mit.edu Organization: MIT Artificial Intelligence Laboratory, Concurrent VLSI Architecture Lines: 25 In article raje@lattice.stanford.edu (Prasad Raje) writes: >The cell size must get smaller, but the cell capacitance cannot. >Why? >You need a large enough cell capacitance to guard against soft errors due >to radiation. That is you need to store at some minimum number of electrons >per cell. These days this number is in the few tens of thousands of electrons. An interesting note: Don Speck, in his paper at the '91 Santa Cruz VLSI conference had a paper about a DRAM design that he built for the MOSIAC project at Caltech. He did a bit of investigation of radiation effects, and found evidence indicating that this argument might not be correct. The idea is that the radiation hit creates some number of electron-hole pairs that could corrupt the state of the capacitor. However, the charged-pair creation happens below the surface of the chip, so that by the time they diffuse up, they've also spread. So the amount of corrupting charge becomes a function of the area of the capacitor (since the diffused area is much larger than a capacitor). As the size of the cell decreases, the amount of the charge on the cell decrease, but so does the amount of charge intercepted. It was a nice paper. I'd recommend it.