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From: clc5q@hemlock.cs.Virginia.EDU (Clark L. Coleman)
Newsgroups: comp.arch
Subject: CISC MIPS/MHz Again
Message-ID: <1991May16.182143.15390@murdoch.acc.Virginia.EDU>
Date: 16 May 91 18:21:43 GMT
Sender: usenet@murdoch.acc.Virginia.EDU
Reply-To: clc5q@hemlock.cs.Virginia.EDU (Clark L. Coleman)
Organization: University of Virginia Computer Science Department
Lines: 16

The April 29, 1991 EE Times, page 16, mentions a 33-MHz TRON micro
from Fujitsu that supposedly runs at 32 MIPS. No benchmark explanation.
It is not intended for workstations, so we will probably never see
SPEC results for it, and it won't be sold in the U.S. But I am curious
to find out if anyone knows anything about the chip and the extremely
high ratio of 32 MIPS to 33 MHz for a CISC chip. It has an on-chip cache
of 2 KB and is described as "a five-pipeline CISC processor" that is
"capable of multitasking", "32-bits", and "developed to run the TRON
operating system or Unix."

Clever design or another meaningless "MIPS" claim?

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"The use of COBOL cripples the mind; its teaching should, therefore, be 
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|||  clc5q@virginia.edu (Clark L. Coleman)