Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!uwm.edu!ogicse!cvedc!mcspdx!adpplz!martin
From: martin@adpplz.UUCP (Martin Golding)
Newsgroups: comp.arch
Subject: Re: VISC - A way to speed up moto cisc mpu's?
Message-ID: <744@adpplz.UUCP>
Date: 16 May 91 18:30:39 GMT
References: <1991May15.110000.25800@Daisy.EE.UND.AC.ZA>
Organization: ADP Dealer Services R&D, Portland, OR
Lines: 25

In <1991May15.110000.25800@Daisy.EE.UND.AC.ZA> mcdonald@Daisy.EE.UND.AC.ZA (Bruce J McDonald) writes:

>Variant Instruction Set Computers - VISC
>----------------------------------------
[description of hypothetical future machine with 64 bit risc and 68xxx modes]

Mode switching is Vax. Extending the instruction set is Eagle. 
Plus ca change, plus ce la meme chose (My French is as good as my c).
For the MOST exciting variable instruction set, consider the Burroughs
1700, with a byte width of 1, a variable word width up to 24, and microcode
swapping to adapt the instruction set to the program that was running.
(PROOF that Cobol isn't a real language: on the B1700, Cobol and RPG ran
on the _same virtual machine_. Peugh.)

And while we're busy making current computers into oldfashioned computers:
Don't forget the Cyber trick of running multiple tasks on multiple
memory buses with a single CPU (adapt cheap memory to fast RISC chips)
or the IBM fancy that decoded 360 instructions for a dataflow processor
(For some instruction sequences, dataflow beats scoreboard).


Martin Golding    | sync, sync, sync, sank ... sunk:
Dod #0236         |  He who steals my code steals trash.
A poor old decrepit Pick programmer. Sympathize at:
{mcspdx,pdxgate}!adpplz!martin or martin@adpplz.uucp