Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sdd.hp.com!zaphod.mps.ohio-state.edu!samsung!munnari.oz.au!cs.mu.OZ.AU!pkl From: pkl@ee.mu.OZ.AU (Peter LAWREY) Newsgroups: comp.arch Subject: Re: Three Address vs Two Address Architectures Message-ID: <1991May16.235124.14253@mulga.cs.mu.OZ.AU> Date: 16 May 91 23:51:24 GMT References: <1991May3.142835.9196@webo.dg.com> <21296@cbmvax.commodore.com> Sender: news@cs.mu.OZ.AU Organization: University of Melbourne, EE Engineering Lines: 18 In article <21296@cbmvax.commodore.com> jesup@cbmvax.commodore.com (Randell Jesup) writes: >In article spot@CS.CMU.EDU (Scott Draves) writes: >>As far as i can tell, on a typical RISC machine, the biggest (only?) >>advantage to 2-address ops is it saves you instruction bits. > > The RPM-40 did this in order to get 16 bit instructions. > >>what if you made a machine with two sorts of every op: one that was >>2-address, and one that was 3-address. The two address ones could >>access only part of the register file. Why not use a mixed system? Ie Four registers in a 32-bit instruction which allows two formats eg. (Where R0 is always 0). A opcode dest1,src1,dest2,src2 : This allows a virtual 2 16-bit instructions opcode dest ,src1,R0 ,src2 : Acts as a 32-bit 3 operand instruction. This does however put a server restiction on the number and size of opcodes. However most of the common arithmetic opcodes can be covered. eg add,move,cmp. Even with 4 operands of 5 bits each this leaves 12 bits for the opcode (and space for other formats).