Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!elroy.jpl.nasa.gov!lll-winken!llnl!tazdevil!brooks From: brooks@tazdevil.llnl.gov (Eugene D. Brooks III) Newsgroups: comp.arch Subject: Re: Anything wrong with the i860 Message-ID: <848@llnl.LLNL.GOV> Date: 17 May 91 05:33:34 GMT References: <3986@ssc-bee.ssc-vax.UUCP> <1991May16.221437.10751@rice.edu> Sender: news@llnl.LLNL.GOV Organization: Lawrence Livermore National Laboratory Lines: 25 In article <1991May16.221437.10751@rice.edu> preston@ariel.rice.edu (Preston Briggs) writes: >The i860 can smoke a Sparc, but it takes a smart (mostly non-existant) >compiler and the right applications. A man at Alliant charactarized >the 860 as having a small "sweet spot". The "sweet spot" of the i860, 4 K bytes, is indeed very small. That the chip is so difficult to compile for indicates a poorly designed architecture. The "sweet spot" of several more recently available micros, IBM's and HP's, is much larger with data caches of 128 K bytes. Sweet spots which are 32 times larger are definitely better. The "sweet spot" of a true supercomputer ranges in the hundreds of megawords. Sweet spots which are more than a thousand times larger are better, but not always a thousand times better. It is clear that the fundamental problem with leading edge micros today is when they miss their sweet spot they go hungry. In time, micro vendors and memory chip vendors will get together and provide DRAM chips with the internal latches required to interleave memory on a chip. Then the micro's sweet spot will in the same size class as that of a supercomputer and the conventional supercomputer will move on to complete extinction. By then, the i860 and all the other micros lacking some form of explicit vector functionality to saturate the available memory bandwidth will be fodder for lawn sprinkler controllers.