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From: preston@ariel.rice.edu (Preston Briggs)
Newsgroups: comp.arch
Subject: Re: VISC - A way to speed up moto cisc mpu's?
Message-ID: <1991May17.180443.27459@rice.edu>
Date: 17 May 91 18:04:43 GMT
References: <1991May15.110000.25800@Daisy.EE.UND.AC.ZA> <2786@lee.SEAS.UCLA.EDU>
Sender: news@rice.edu (News)
Organization: Rice University, Houston
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plinio@turing.seas.ucla.edu (Plinio Barbeito) writes:

>Does having a RISC core in itself guarantee fast execution?  I thought
>the reason RISC was fast was the great amount of space it freed up on
>the chip that could be used to speed up basic operations.
>
>I think it would be more in line with RISC philosophy to rip out as
>much of the CISC core as possible, leaving close to the bare minimum of 
>what is needed to emulate via software traps those addressing modes that 
>would be deleted (most) and those instructions that would be deleted 
>(anything that compilers are staying away from, up to the neck of the 
>curve).

I think an important part of the "risc philosophy" is to expose low
level operation to the compiler.  If you bundle them up into
cisc-like globs, the optimizer loses many opportunities.

Emulation should probably be restricted to maintaining object compatibility,
with the understanding the recompilation is always preferable, in terms
of performance.

Preston Briggs