Newsgroups: comp.realtime
Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!wuarchive!m.cs.uiuc.edu!gillies
From: gillies@m.cs.uiuc.edu (Don Gillies)
Subject: Re: What is the future of realtime and RISC?
Message-ID: <1991May17.170601.26095@m.cs.uiuc.edu>
Organization: University of Illinois, Dept. of Comp. Sci., Urbana, IL
References: <1991May15.210430.1134@nbc1.ge.com> <23089@ists.ists.ca>
Date: Fri, 17 May 1991 17:06:01 GMT

georg@sgl (Georg Feil) writes:

>-With RISC fanciness such as delayed branches and greater reliance on 
>   caching, the hard determinism required in many real-time applications 
>   is more difficult to come by.

I disagree with this.  RISC processors are much more deterministic
than previous-generation CISC processors.  Nearly all instructions in
RISC architectures such as MIPS have a latency of 5 cycles and take
exactly 1 cycle to execute.  The latency of delayed branches is
completely predictable.  Memory fetches must be (somewhat) aligned, so
that loads takes exactly two cycles to execute.

I fail to see how RISC machines rely more on cacheing than CISC
machines.  Give me a RISC and a CISC with identical memory systems and
identical SPECmark, and I think you'll find the caching is greater on
the CISC.

On the other hand, machines line the modes 68020 are highly unsuitable
for real-time systems, because the performance gap between best-case
and worst-case performance can often be a factor of 3-4, even for
straight-line code.  When you have a 3-4 times performance hit in the
worst case, you might as well use a 68000.

Don Gillies	     |  University of Illinois at Urbana-Champaign
gillies@cs.uiuc.edu  |  Digital Computer Lab, 1304 W. Springfield, Urbana IL
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"WAR!  UGH! ... What is it GOOD FOR?  ABSOLUTELY NOTHING!"  
	- the song "WAR" by Edwin Starr, circa 1971


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