Newsgroups: comp.realtime
Path: utzoo!utgpu!cunews!bnrgate!bigsur!bcars434!mcgregr
From: mcgregr@bcars434.uucp (Andrew McGregor)
Subject: Re: What is the future of realtime and RISC?
Message-ID: <1991May18.035926.23378@bigsur.uucp>
Summary: The future may be a scary place
Sender: news@bigsur.uucp
Organization: Bell-Northern Research, Ottawa, Canada
References: <1991May15.210430.1134@nbc1.ge.com> <23089@ists.ists.ca> <1991May17.170601.26095@m.cs.uiuc.edu>
Date: Sat, 18 May 91 03:59:26 GMT

In article <1991May17.170601.26095@m.cs.uiuc.edu> gillies@m.cs.uiuc.edu (Don Gillies) writes:
>
>georg@sgl (Georg Feil) writes:
>
>>-With RISC fanciness such as delayed branches and greater reliance on 
>>   caching, the hard determinism required in many real-time applications 
>>   is more difficult to come by.
>
>I disagree with this.  RISC processors are much more deterministic
>than previous-generation CISC processors.  Nearly all instructions in

In the case of the 80960 some of our people had an interesting experience.
Some measurements on finished code indicated that interrupts were taking
2-3 times longer than spec.  Much hairy analysis later they realized
that the idle loop of the software tended to queue several memory 
accesses into a slow area of RAM so that when the interrupt hit and the
state had to change the interrupt was delayed until all outstanding
memory accesses had completed.

I'm inclined to agree with the first poster that a RISC chip will tend
to be hairier, mostly because of what they do with all the extra real 
estate (superscalar stuff, register windows, etc...)

Andrew McGregor (MCGREGR@BNR.CA)	Phone:	(613) 763-7236
Bell-Northern Research		
P.O. Box 3511, Station C, Ottawa, Ontario, Canada, K1Y 4H7

--
Andrew McGregor (MCGREGR@BNR.CA)	Phone:	(613) 763-7236
Bell-Northern Research		
P.O. Box 3511, Station C, Ottawa, Ontario, Canada, K1Y 4H7