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From: csuwr@warwick.ac.uk (Derek Hunter)
Newsgroups: comp.sys.acorn
Subject: 32bit immediate load in ARM code
Message-ID: <+|Q_L||@warwick.ac.uk>
Date: 16 May 91 05:35:57 GMT
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I was trying to cut down the number of labels my C compiler produces,
 (having finally allowed the thing to access globals beyond the 4095 range),
 and I (re)invented this:

You can do 	Ldr Rn,VERY_FAR_AWAY	; with:

		Ldr Rn,[PC]
		Ldr Rn,[PC,Rn]
		DCD VERY_FAR_AWAY-P%	; if V_F_A preceeds this code

		Ldr Rn,[PC]
		Ldr Rn,[PC,-Rn]		;   (You /can/ do -Rn, can't you?)
		DCD P%-VERY_FAR_AWAY    ; if it doesn't

	. . . and they are still relative addresses cunningly enough.
		(In fact, I think they exceed the addressing space!)

32 bit immediate constants can be read with

		Ldr Rn,[PC]
		Bic Rn,Rn,# (( number >> 28 ) EOR 15) << 28
		DCD number OR &F0000000

            or equivalent, (but Bic impresses people, because no-one knows
                            what it does, and those shift-28s are luvverly).

(If you didn't guess, the DCDs are all -ve and the top nybble is set to &F
 making the DCD value pretend to be an op code with the NeVer condition set
 so the processor can run through it without so much as an `undefined
 instruction', unless someone's been *really* dense and told it to complain
 on UndefinedNV. Blast! That's potentially spoiled my whole strategy!
 Is it OK for top /byte/ = &FF?)

I don't know whether this is well known and/or despised, but it seemed like
 quite a good trick at the time.

My main point of interest is this: On an ARM 3, would the DCD be read into
 cache in an s cycle during the final stage of the Ldr Rn,[PC], or does it
 take an n cycle all of its very own?

                   Is this nice on an ARM 3's cache?

                           Is it nice at all?

                   Was this the intentional use of NV?

                           Has Acorn used it?     

                 Is the UndefinedNV really a problem?

   Will this latter be supported in future releases of the hardware?


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