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From: nbvs@cl.cam.ac.uk (Nicko van Someren)
Newsgroups: comp.sys.acorn
Subject: Re: 32bit immediate load in ARM code
Message-ID: <1991May16.162053.13258@cl.cam.ac.uk>
Date: 16 May 91 16:20:53 GMT
References: <+|Q_L||@warwick.ac.uk>
Reply-To: nbvs@cl.cam.ac.uk (Nicko van Someren)
Organization: U of Cambridge Comp Lab, UK
Lines: 32

In article <+|Q_L||@warwick.ac.uk> csuwr@warwick.ac.uk (Derek Hunter) writes:
>My main point of interest is this: On an ARM 3, would the DCD be read into
> cache in an s cycle during the final stage of the Ldr Rn,[PC], or does it
> take an n cycle all of its very own?
>
>                   Is this nice on an ARM 3's cache?
>
>                           Is it nice at all?
>
>                   Was this the intentional use of NV?
>
>                           Has Acorn used it?     
>
>                 Is the UndefinedNV really a problem?
>
>   Will this latter be supported in future releases of the hardware?

Indeed, on an ARM3 the constant will get cached bacause the cache always reads
in 'lines' of four words.  Since by the time the LDR instruction is being
the other end of the pipeline will be being loaded with the NeVer instruction
the data must be in the cache and no extra external cycles will happen on an
ARM3.  IMHO it is nice on a cache, nice at all, a useful use of NV but I don't
know if Acorn have used it. I think if you read the chip spec carefully
you will find aborts can only occur on instructions with valid condition codes.
Having said that, I bet they will remove the NV option on future chips just to
wind us up. After all, if you look at the statistics compilers never use that
option so they might as well take it out!

Nicko
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| Nicko van Someren, nbvs@cl.cam.ac.uk, (44) 223 358707 or (44) 860 498903    |
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