Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!mips!dimacs.rutgers.edu!rutgers!cbmvax!cbmehq!babylon!rbabel
From: rbabel@babylon.rmt.sub.org (Ralph Babel)
Newsgroups: comp.sys.amiga.hardware
Subject: Re: SIMM Modules
Message-ID: <07915.AA07915@babylon.rmt.sub.org>
Date: 15 May 91 01:23:04 GMT
References: <1701@giaea.gi.oz> <mmm.1221@reaper.Chi.IL.US> <1098@zds-oem.UUCP>
Reply-To: cbmvax.commodore.com!cbmehq!babylon!rbabel (Ralph Babel)
Lines: 31

In article <1098@zds-oem.UUCP>, easton@zds-oem.UUCP (Jeff
Easton) writes:

> The new x32 SIMM's used in the GVP '030 accelerators are
> another story. They appear to be proprietary unto GVP and
> do not follow the JEDEC x32 (x36) standard.  How they get
> a 32 bit wide SIMM in a standard 30 pin SIMM socket is
> beyond my comprehension.  Maybe Ralph can comment on this
> one?

32-bit-wide SIMMs in a 30-pin socket? This would indeed be a
nice trick! :-) No, it's really 64 pins. (And I really like
the new SIMM sockets used by GVP! Well, I probably have to
change SIMMs more often than most people.)

I've been told that they designed their own 32-bit-wide SIMM
because: (a) there was no accepted standard at that time;
and (b) they wanted to include some "sense" pins to get rid
of almost all of those memory configuration jumpers. The new
"all-in-one" accelerator board, for example, has only two
memory jumpers left, mainly to decide whether to configure
the SIMMs as Zorro-II or "Extended" (beyond $00ffffff) RAM.

I don't know whether or not this is true. I don't know how
much of a standard the JEDECx32 SIMMs are or if there are
other "standards" around. I don't know if those JEDEC SIMMs
also include pins that could be used by the RAM controller
hardware to automatically sense the presence of a SIMM.
So please correct me if I'm wrong.

Ralph