Path: utzoo!utgpu!cunews!bnrgate!bigsur!bnr-rsc!mascot@bnr.ca
From: mascot@bnr.ca (Scott Mason)
Newsgroups: comp.sys.amiga.hardware
Subject: Re: A3000: 16MHz vs. 25MHz
Message-ID: <4520@bnr-rsc.UUCP>
Date: 16 May 91 19:13:30 GMT
References: <1991May11.150058.4684@vax5.cit.cornell.edu> <4502@bnr-rsc.UUCP> <21601@cbmvax.commodore.com>
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In article <21601@cbmvax.commodore.com> daveh@cbmvax.commodore.com (Dave Haynie) writes:
>In article <4502@bnr-rsc.UUCP> mascot@bnr.ca (Scott Mason) writes:
>>In article <1991May11.150058.4684@vax5.cit.cornell.edu> kzyx@vax5.cit.cornell.edu writes:
>
>>>	I wonder how much I have to change to get a 25 MHz 040 in a 16MHz
>>>stock A3000.
>
>>The 68040 implements a very different bus interface from the 68030.
>>The amount of logic required to interface an 040 to a 68000 or
>>68030 slave is nontrivial.
>
>Well, that's a matter of what you consider trivial.  It's certainly not a "do
>it yourself" exercise, unless you're an experienced hardware hacker.  It's also
>not earthshakingly hard, either.  The bus conversion logic for 68030->68000,
>68040->68000, or 68040->68030, is typically a couple of PALs and a handful of
>buffer chips.  A designer can increase the performance of such a system by
>adding more logic, but a basic converter isn't very difficult.  In fact, when
>the 68040 stuff first came out, Motorola published an application note on how
>to convert a 68040 bus to a 68030 bus.  I don't know if it's an optimal design,
>but it does appear to work.

Dave, IMHO you are understating the case. The 68030 is not that different
from the 68000 in the bus interface that it implements. A little 
combinatorial logic to translate the slightly different control signals
and synchronizers for a few control signals are about all one would need.

The bus protocol of the 68040 is significantly different from the '030
and '020. One basically ends up implementing the entire bus interface
logic of the '030. As mentioned in the Motorola app. note that you site:

  - support for an asynchronous interace
  - dynamic bus sizing for 8-, 16-, and 32-bit ports (ed: biggie !!)
  - retry mechanism handled independantly of the 68040
  - the bus arbitration protocol of the '020 (ed: or '030) emulated

The first thing they drop down is a DMA controller, since the bus
adapter may need to execute several slave bus cycles for one '040
access. All told they use:

  - 6 PALs
  - a phase-locked loop
  - upwards of 10 octal buffers
  - upwards of *115* external signals just for the bus adapter

The '040 model for the external interface is significantly more
advanced in some areas, such as multiprocessor support, than the '030,
but it is correspondingly different. Some of the changes, such as
dynamic bus sizing support, are probably because the rich '030
features were really dragging down the performance.

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