Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!jarthur!uunet!overload!dillon From: dillon@overload.Berkeley.CA.US (Matthew Dillon) Newsgroups: comp.sys.amiga.programmer Subject: Re: Short Hello World Message-ID: Date: 15 May 91 19:28:53 GMT References: <1804@tardis.Tymnet.COM> <1991May7.001146.1830@cinnet.com> <1991May10.103117.4270@cs.umu.se> <1991May11.072139.781@starnet.uucp> <1991May14.041050.20607@starnet.uucp> Organization: Not an Organization Lines: 27 In article <1991May14.041050.20607@starnet.uucp> sschaem@starnet.uucp (Stephan Schaem) writes: > > > Are you telling me that clr.w d0 dont take 4 cycle?! > And If I use clr its when I dont want to modify any register and dont > care about speed but size... > > > Stephan. CLR.W D0 ; 4 CLR.L D0 ; 6 MOVEQ #0,D0 ; 4 CLR.W memory ; 4+4+4=12 (not incl. effective addr calc) CLR.L memory ; 4+8+8=20 Remember, the 68000 handbook is *wrong* -Matt -- Matthew Dillon dillon@Overload.Berkeley.CA.US 891 Regal Rd. uunet.uu.net!overload!dillon Berkeley, Ca. 94708 USA