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From: cprice@mips.com (Charlie Price)
Newsgroups: comp.sys.mips
Subject: Re: mflo/mfhi interlock length
Message-ID: <3581@spim.mips.COM>
Date: 16 May 91 20:34:09 GMT
References: <1991May14.164323.20809@cs.cornell.edu>
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In article <1991May14.164323.20809@cs.cornell.edu> charney@CS.Cornell.EDU (Mark Charney) writes:
>
>
>What is the length of the interlocks after mult,multu,div,divu
>on the R2000/R3000? 
>
>Kane's _MIPS_RISC_Architecure_ says 10 and 11 cycles 
>(pages C-10,C-11) for multu. Are both correct?
>
>The examples are:
>Page C-10:
>	multu	a0, a3
>		# 10 cycles
>	mflo	t0
>
>Page C-11:
>	multu	t4, t6
>		# 11 cycles
>	mflo	t0
>	mfhi	t1
>

I would guess that the comments in the code fragments are wrong.

The number of cycles required between a MULT, MULTU, DIV or DIVU operation
and a subsequent MFHI or MFLO operation in order that no interlock
occurs is:

		MULT	MULTU	DIV	DIVU
R2000/R3000	 12	 12	35	35
R6000		 17	 18	38	37
-- 
Charlie Price    cprice@mips.mips.com        (408) 720-1700
MIPS Computer Systems / 928 Arques Ave.  MS 1-03 / Sunnyvale, CA   94088-3650