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From: alan@uh.msc.umn.edu (Alan Klietz)
Newsgroups: comp.arch
Subject: Re: Anything wrong with the i860
Message-ID: <4128@uc.msc.umn.edu>
Date: 20 May 91 18:55:34 GMT
Article-I.D.: uc.4128
References: <3986@ssc-bee.ssc-vax.UUCP> <dank.674423728@blacks> <1991May16.221437.10751@rice.edu> <848@llnl.LLNL.GOV>
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Reply-To: alan@msc.edu (Alan Klietz)
Organization: Minnesota Supercomputer Center, Minneapolis, MN
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In article <848@llnl.LLNL.GOV> brooks@tazdevil.llnl.gov (Eugene D. Brooks III) writes:
<The "sweet spot" of the i860, 4 K bytes, is indeed very small.
<That the chip is so difficult to compile for indicates a poorly designed architecture.

Another difficulty is the lack of registers.  A trivial application
like a vector sum requires 7 registers.  With more than a few vector
operands you quickly run out of registers for pipelines, and then have to
either stall to reuse registers or else break the vector expression into
chunks and stream them in and out of memory, tripling the memory bandwidth
requirement.

--
Alan E. Klietz
Minnesota Supercomputer Center, Inc.
1200 Washington Avenue South
Minneapolis, MN  55415
Ph: +1 612 626 1737	       Internet: alan@msc.edu