Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!dali.cs.montana.edu!uakari.primate.wisc.edu!zaphod.mps.ohio-state.edu!pacific.mps.ohio-state.edu!linac!midway!quads.uchicago.edu!rtp1 From: rtp1@quads.uchicago.edu (raymond thomas pierrehumbert) Newsgroups: comp.arch Subject: Re: Anything wrong with the i860 Message-ID: <1991May21.034145.16107@midway.uchicago.edu> Date: 21 May 91 03:41:45 GMT References: <848@llnl.LLNL.GOV> <1991May16.221437.10751@rice.edu> <4690@alliant.Alliant.COM> Sender: news@midway.uchicago.edu (NewsMistress) Organization: University of Chicago Lines: 36 >(jgreen of Alliant writes about the performance of the >FX/2800, which uses the i860) This summary may sound a little 'boosterish', so I thought I'd chime in, as a user, that I have been considering the FX/800, and done extensive benchmarks; the thing really does perform as advertised, and if the are any "gotchas" I haven't found them yet. On a lot of scientific codes I have been using, the performance of a detached processor in the Alliant runs at about the speed of an IBM RS/6000 model 530, which I think is pretty good, given that you have 8 processors in the thing. There does seem to be some problem with the onboard chip cache in a parallel environment. In going from running code on a detached processor to running parallel,you have to disable the onboard cache. This is a big performance hit, and has the result that running parallel on two processors often isn't a whole lot faster than running detached on a single processor. You see big performance gains by the time you get up to four processors in parallel, but on an FX/800, that is your limit of how many processors you can normally use on a job (because of memory bandwidth). In hand-coded routines, like their FFT, Alliant manages to use the onboard cache even in a parallel situation, but maintaining cache-coherency through clever tricks. This trick also lets them use all 8 processors in parallel (given that there is a lot of data re-use in the FFT). Chip mods to the i860 that allowed compilers to find this kind of thing would greatly enhance the utility of the chip. Basically, I think it is POSSIBLE to write a good compiler for the chip, and Alliant has more or less done it, but the extremes to which they had to go suggest also that there are some design flaws in the i860.