Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!think.com!spool.mu.edu!cs.umn.edu!kksys!edgar!orac!bret
From: bret@orac.UUCP (Bret Indrelee)
Newsgroups: comp.arch
Subject: Re: Atomic operations
Summary: Give me CAS
Keywords: atomic access, CAS
Message-ID: <309@orac.UUCP>
Date: 19 May 91 05:39:14 GMT
Article-I.D.: orac.309
References: <1991Apr22.175410.9840@decvax.dec.com> <1991May2.201917.15062@dg-rtp.dg.com> <1991May6.113149.14531@decvax.dec.com>
Organization: Technix Inc., Saint Paul MN, USA
Lines: 25

>kenton@abyss.zk3.dec.com (Jeff Kenton OSG/UEG) writes:

>Once you've created a lock (with xmem) you can do almost anything within the
>locked region of code without disabling interrupts.
>

So let me see if I have this right?  Instead of a Compare-And-Swap, you
would compete for a lock bit, do your atomic instruction, and then release
the lock bit?

I would much rather have the CAS in hardware.  With CAS, you can emulate
the other common atomic accesses (Test and Set, Fetch and Add, parallel
linked list manipulation, and the list goes on) without need for a
special lock bit on the data.

The importance of atomic accesses is even more important when you
start putting more than one processor into a single system.
I kind of like being able to manipulate linked lists without having
to lock the whole list.

-Bret
-- 
------------------------------------------------------------------------------
Bret Indrelee		|	<This space left intentionally blink>
bret@orac.edgar.mn.org	|					;^)