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From: jbs@WATSON.IBM.COM
Newsgroups: comp.arch
Subject: ieee floating standard
Message-ID: <9105220041.AA14355@ucbvax.Berkeley.EDU>
Date: 22 May 91 00:20:38 GMT
Sender: daemon@ucbvax.BERKELEY.EDU
Lines: 22


         Richard O'Keefe says:
Given that the same posting has already beaten Herman Rubin over the
head with the IEEE standard, this doesn't go down well.  IEEE extended
precision (and the IEEE standard does recommend that it be provided)
uses 64-bit signifcands, so a "full" implementation of IEEE 754 would
include a 64x64 multiplier, not a 53x53 one.  Don't the 80387 and the
68882 chips offer extended precision?  What size of multiplier do they
use?

         Let me explain what I meant.  When I stated that the IEEE
standard has become so entrenched that manufacturers are effective-
ly forced to use it, I was referring primarily to the representa-
tion of 32 and 64 bit floating point numbers and secondarily to the
way floating arithmetic (in round to nearest mode) is defined to
work.  I do not believe the entire standard is so entrenched.
         In any case, is it not the case that the IEEE standard for
extended requires at least 64 bits in the fraction (not 64 bits)?
If so a 128 bit format (a much more sensible length than 80) with
106 bit fractions could utilize a 53X53 multiplier.  Also does the
standard recommend that extended be provided in hardware?
                        James B. Shearer