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From: p554mve@mpirbn.mpifr-bonn.mpg.de (Michael van Elst)
Newsgroups: comp.sys.amiga.hardware
Subject: Re: Breaking through the chip-bus barrier?
Message-ID: <2058@mpirbn.mpifr-bonn.mpg.de>
Date: 19 May 91 15:41:21 GMT
Article-I.D.: mpirbn.2058
References: <ajbrouw.3618@ecl001.UUCP>
Reply-To: p554mve@mpirbn.UUCP (Michael van Elst)
Organization: Max-Planck-Institut fuer Radioastronomie, Bonn
Lines: 24

In article <ajbrouw.3618@ecl001.UUCP> ajbrouw@ecl001.UUCP (Albert-Jan Brouwer) writes:
>Imagine a new Denise (graphics chip) that would snoop the chip bus and
>maintain a mirror copy of the entire chip memory range. F.e. a small
>board that plugs into the Denise socket and sport the new Denise and
>2MB DRAM. All writes to chip memory would get copied into the mirror
>chip memory. The new Denise could then fetch all bitplane data from this
>mirror memory without taxing the chip bus.

Surely possible but it is much easier to use VRAMs for that. Instead of
generating chip bus cycles to fetch display data one uses the shift
registers. Of course this has the problem that one can't interleave
the cycles for the bitplanes. One would need an extra scanline buffer
to gather all bits for a line before sending them to the palette.
This is a bit similar to one of the Intel graphics processors (82768 ?)
although this one didn't use dual-ported RAMs.
This technique would have a second consequence: the cycle time would
be independant of the video shift frequency.

Regards,
-- 
Michael van Elst
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Internet: p554mve@mpirbn.mpifr-bonn.mpg.de
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