Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!wuarchive!rex!spool.mu.edu!munnari.oz.au!diemen!tasman!steveh From: steveh@tasman.cc.utas.edu.au (Steven Howell) Newsgroups: comp.sys.m68k Subject: Bus Request & Isolation On The 68000 Message-ID: Date: 19 May 91 07:32:21 GMT Sender: news@diemen.utas.edu.au Distribution: comp Lines: 45 Cheers Folks A question I have, that you just may be able to help me out with. I have been putting together a simple accelerator for our MC68000 Based prototype mini workstation. The Boards have been completed, but somewhat few months behind schedule, and I wish to accelerate their processing performace by replacing the 68000 with the now readily avail nice price power house 68000/16 or 68020/25. The simplicity of replacing the chip at board level crossed my mind, but was shattered when I realised I had to divide a heap of timing signals to ensure compatibility with the SCC, Video, Sound and HD/Floppy disk Interfaces. So, I had an Idea... I am fairly sure of what needs to be done, but somewhat in doubt. Maybe some one who has had experience with this sort of interface could help me. I wish to send a Bus request (-BR) signal to processor, so that it will release the CPU, to another CPU. Namely the faster 68000 or 68020. I understand that (according to my motorola reference manuals) if i send a (-BR), it will accept, and issue a bus grant signal (-BG), indicating the cpu has released the bus to the next bus master requesting it.(when it finishes its last cycle). What actually happens to CPU when this condition has been met. Does it go high impedance, and can another processor replace all signals except clock in this condition. Can another CPU replace all current I/O and operate without any clashes at a higher speeds. Is it only the buses (address&data) that are released to another Bus master. Can i remain permanantly in this state after invoking it. Can anyone please help me out on this. Thanks In Advance Steveh