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From: icsu8053@khan.cs.montana.edu (Craig Pratt)
Newsgroups: sci.electronics,comp.unix.questions,comp.unix.wizards
Subject: Determining gate depth & critical timing w/OCT tools
Summary: How do you get gate timing info from an OCT design?
Keywords: digital OCT critical timing gate depth MSU cells
Message-ID: <3971@dali>
Date: 17 May 91 02:34:14 GMT
Sender: usenet@dali.cs.montana.edu
Followup-To: sci.electronics
Organization: Montana State University, Dept. of Computer Science, Bozeman MT 59717
Lines: 12

How can one determine the total gate delay of the critical path and gate 
depth of an OCT tools design?  (Besides constructing the circuit by hand from 
the BDNet file.)  I'm new to the OCT tools, and am not familiar with many
of its features.  I do know that we are using the Mississippi standard cell
library and that some obscure OCT tools are missing due to Ultrix incom-
patabilities.  *Any* recommendations are appreciated.

--
 Craig Pratt                                           icsu8053@cs.montana.edu
 Montana State University, Bozeman MT        Craig.Pratt@msu3.oscs.montana.edu
 "It's a Buddist meditation technique; it focuses your aggression.  The monks
  used to do it before they went into battle.", Otto, _A_Fish_Called_Wanda_