Path: utzoo!utgpu!news-server.csri.toronto.edu!bonnie.concordia.ca!nstn.ns.ca!news.cs.indiana.edu!samsung!usc!rpi!uupsi!ficc!peter From: peter@ficc.ferranti.com (peter da silva) Newsgroups: comp.arch Subject: Re: new instructions Message-ID: Date: 23 May 91 12:38:05 GMT References: <1991May22.001620.751@craycos.com> <1991May23.084258.5062@kithrup.COM> <24216@lanl.gov> Organization: Ferranti International Controls Corporation Lines: 19 In article <24216@lanl.gov>, jlg@cochiti.lanl.gov (Jim Giles) writes: > Leading zero count is a 3 clock instruction. I doubt that could be > implemented in fewer clocks than the pop count if you did it with a > table. I suspect it could. You would only have to do a table-lookup on the first non-zero byte. You could even use binary search techniques to reduce the number of compares with zero. But the question isn't whether you can do these operations in software anywhere near as fast as they can be done in hardware, but rather whether they can be done fast enough. That is, how much faster would applications that make heavy use of these instructions run if you sped them up by a factor of 10 (which is about what I would have guessed the speed difference to be)? If you speed up 3% of the program by a factor of 10, it's pretty much lost in the noise. -- Peter da Silva; Ferranti International Controls Corporation; +1 713 274 5180; Sugar Land, TX 77487-5012; `-_-' "Have you hugged your wolf, today?"