Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sdd.hp.com!mips!sgi!shinobu!rodman
From: rodman@sgi.com (Paul K. Rodman)
Newsgroups: comp.arch
Subject: Re: CISC MIPS/MHz Again
Message-ID: <1991May23.175200.13005@shinobu.sgi.com>
Date: 23 May 91 17:52:00 GMT
References: <1991May16.182143.15390@murdoch.acc.Virginia.EDU> <YUHARA.91May20200857@kiko.stars.flab.fujitsu.co.jp>
Sender: news@shinobu.sgi.com (Net News)
Organization: Silicon Graphics, Inc., Mountain View, CA
Lines: 24

In article <YUHARA.91May20200857@kiko.stars.flab.fujitsu.co.jp> yuhara@kiko.stars.flab.fujitsu.co.jp (Masanobu Yuhara) writes:
>
>TRON instruction set is very CISCy, but this chip was designed RISCy.
>i.e. most primitive instructions run in one cycle (if cache hits) including:
>	add @(offset:32,R1), R2		; R2 += memory(R1 + 32_bit_offset) 
>

I worked on high-end CISC machines a decade ago that could even do:

             reg += memory(reg + reg + offset) 

in one cycle. (assuming cache hits) This is called "designing a
high-end machine that isn't worthless", not RISCy design, IMHO....:-)







--
Paul K. Rodman                                     Advanced Systems Division
rodman@sgi.com                                     Silicon Graphics, Inc.
   KA1ZA                                           Mountain View, Ca.