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From: gl8f@astsun9.astro.Virginia.EDU (Greg Lindahl)
Newsgroups: comp.arch
Subject: what if the i860 had vector registers... ?
Message-ID: <1991May24.035756.5161@murdoch.acc.Virginia.EDU>
Date: 24 May 91 03:57:56 GMT
Sender: usenet@murdoch.acc.Virginia.EDU
Organization: Department of Astronomy, University of Virginia
Lines: 15

After reading a tech report on i860 performance (available from
uvacs.cs.virginia.edu: pub/techreports/ipc...), I was left with one
question:

The i860 has an 8k data cache, and both normal loads and pipelined
loads that avoid the data cache. It seems to be very nasty to write a
compiler that can do the right thing, with the particular memory
system that Intel put in the iPSC i860 machine (page mode DRAM).

So, what if the i860 instead had a small data cache, and pipelined
loads into vector registers? It is relatively easy to design a
compiler that can do a good job with vector registers. And you would
be able to do pipelined loads of data to be re-used. And you wouldn't
end up starved for registers. Did Intel simulate this, or did they
guess? Did they guess wrong?