Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!cadence!cadence.com!berman
From: berman@pebbles.cadence (Victor Berman; x6276)
Newsgroups: comp.lang.vhdl
Subject: Re: EIA/IEEE logic modeling standards
Message-ID: <BERMAN.91May24154508@pebbles.cadence>
Date: 24 May 91 20:45:08 GMT
References: <RAYV.91May17110945@revenge.oakhill.uucp>
Sender: usenet@cadence.com (USENET News)
Distribution: comp.lang.vhdl
Organization: /net/pebbles/home/berman/.organization
Lines: 10
In-Reply-To: rayv@revenge.oakhill.uucp's message of 17 May 91 16:09:45 GMT

The IEEE package is currently the one being looked at as the standard.  The
EIA has agreed to track the IEEE package and divide out those functions which are
not in common into a separate package which will be supplied as a sort of
recommended tool kit but not as part of the required standard.  The issue
of the don't care state which is currently in the IEEE but not in EIA is
still not entirely resolved.  The EIA feels that this state is not appropriate
for actual parts models and may stick with a sub-type excluding this state.

Victor Berman
berman@cadence.com