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From: ssave@ole.UUCP (Shailendra Save)
Newsgroups: comp.lsi.cad,comp.lsi,sci.electronics
Subject: 3.3V v/s 5V
Keywords: Vdd. 3.3v
Message-ID: <1956@ole.UUCP>
Date: 23 May 91 17:51:43 GMT
Organization: Seattle Silicon Corp., Bellevue, WA.
Lines: 16


  In this week's Electronic Engineering Times (May 20th issue)
  there is an article about AT&T developing a 3.3V cell library.
  On pp 16, (bottom 2nd column) they claim:

  The basic 2 input NAND-gate power rating is 6.1uW/MHz at 5V
  dropping to 1.1uW/MHz at 3.3V

  I am missing something here. If it is a CV^2 relationship,
  it should be approx. 2.5 and not 1.1  Could some knowledgeable
  person please tell me how this claim is true? Do they use a
  different process? 

					Shailendra
					ssave@caen.engin.umich.edu
					sumax!ole.uucp!ssave