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From: sllu@maui.cs.ucla.edu (Shih-Lien Lu)
Newsgroups: comp.lsi.cad
Subject: Re: 3.3V v/s 5V
Keywords: Vdd. 3.3v
Message-ID: <1991May25.204213.614@cs.ucla.edu>
Date: 25 May 91 20:42:13 GMT
References: <1956@ole.UUCP> <9577@sail.LABS.TEK.COM>
Sender: Shih-Lien Lu
Organization: UCLA Computer Science Department
Lines: 35
Nntp-Posting-Host: maui.cs.ucla.edu

>In article <1956@ole.UUCP> ssave@ole.UUCP (Shailendra Save) writes:
>>
>>  In this week's Electronic Engineering Times (May 20th issue)
>>  there is an article about AT&T developing a 3.3V cell library.
>>  On pp 16, (bottom 2nd column) they claim:
>>
>>  The basic 2 input NAND-gate power rating is 6.1uW/MHz at 5V
>>  dropping to 1.1uW/MHz at 3.3V
>>
>>  I am missing something here. If it is a CV^2 relationship,
>>  it should be approx. 2.5 and not 1.1
>>
>>					Shailendra
>
>The way these things work is that the charging current available is a
>function of the difference between the power supply voltage and the
>enhacement threshold voltage of the fets.  As you reduce the power
>supply voltage, the circuit gets slower (and ultimately stops working)
>at the same time the uW/Mhz get smaller, ultimately going to zero when
>the fets no longer are turned on at all.
>
>Arnold Frisch
>Tektronix Laboratories

Are you saying that because Id is smaller, the integral of V(t)Id(t) dt
is smaller? How can one work out the integral?

I do not really know the extact AT&T technology. As Shailendra
pointed out that the dynamic power dissipation is a CV^2 relationship.
Is it possible that the C used in the equation is smaller by a factor of ~2.
As I recall the real (somewhat old) "metal-oxide" gate (instead of
the modern polysilicon gate) process has a smaller gate capacitances. 
Is AT&T's process a C"M"OS process? Just curious.

Shih-Lien