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From: swarren@convex.com (Steve Warren)
Newsgroups: comp.sys.amiga.advocacy
Subject: Re: Blitter vs. 040 (was: Computer Architecture question
Message-ID: <1991May24.174930.20090@convex.com>
Date: 24 May 91 17:49:30 GMT
References: <4987@orbit.cts.com>
Sender: usenet@convex.com (news access account)
Organization: CONVEX Computer Corporation, Richardson, Tx., USA
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In article <4987@orbit.cts.com> chucks@pnet51.orb.mn.org (Erik Funkenbusch) writes:
>dvljrt@cs.umu.se (Joakim Rosqvist) writes:
                                 [...]
>>It doesn't need to access chip ram even then. The blitter-control registers
>>are in the $dff area, not in chip ram.

>yes it is, the $dff area is in "psuedo" fast ram area, this area is on the
>chip bus. 
                                 [...]

Then this would be a good candidate for improvements in a redesigned chip set,
yes?  If all coprocessor control registers were implemented in zero-wait-state
static rams with non-blocking dual ports, that would allow a fast procesor to
program all the co-processors on the chip bus at full speed without even
slowing down.  The only thing the processor would have to slow down for would
be when it was copying blocks of data from fast ram into chip ram.

If a new chip set were implemented in a more modern process technology then
these static rams and all the dual-port circuitry could be rolled into the
ASICs.

--
            _.
--Steve   ._||__
  Warren   v\ *|
             V