Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!zaphod.mps.ohio-state.edu!mips!public!valentin From: valentin@public.BTR.COM (Valentin Pepelea) Newsgroups: comp.sys.m68k Subject: Re: 68040 MMU Prog Question Message-ID: <2867@public.BTR.COM> Date: 23 May 91 08:56:14 GMT References: <62390@mcdchg.chg.mcd.mot.com> <19417@sdcc6.ucsd.edu> Organization: BTR Communications, Mtn. View, CA Lines: 48 >In article <62390@mcdchg.chg.mcd.mot.com> heiby@mcdchg.chg.mcd.mot.com (Ron Heiby) writes: > >I have a customer who is trying to convert their application from an >MVME133XT to an MVME165. They have a 68040 MMU related question that >has arisen from their configuration and the requirements of using the >on-chip cache for performance. They have four regions of memory. >1. On-board memory - 4Meg at 0x0, to be cached I&D, copyback >2. A24 VMEbus space - 12Meg just after the end of 1, non-cached >3. A32 VMEbus space - various areas, many megabytes, non-cached >4. On-board resources - high memory, non-cached Sigh, I should read this newsgroup more often. For performance reasons, your priority should be to set up the MMU in such a way that accesses to the 4Meg of physical ram are maximized. I suggest that you use a TT register to transparently translate the lower 16Meg as copyback cacheable. Then construct a translation table to map the A24 VMEbus space into a higher 16Mb block of logical space. Then access that 12Mb block only at its new logical space. Finally, use the second TT register to transparently translate the rest of the universe as non cached. You will thus require a little over 6K of translation tables, but that should be of no concern. Reserving 6K out of 4Mb for translation tables is insignificant. >We had hoped to be able to do something simple, like with transparent >translation registers, but 16Meg seems to be the minimum size for a TT >reg. Perhaps one could be used for everything beyond the first 16Meg? Not quite. No matter how you remap it, the VMEbus 24 space will prevent an entire 2 Gig space to be adequately transparently translated. But for simplicity, you could remap the VMEbus 24 space beyond the 2Gig line address, and use the second TT register to map everyting below it. For example, you could could set the VMEbus24 address at 0x80000000, set TT register 0 to translate the entire first 16Meg block (addr: 0x00 mask: 0x00) and TT register 1 to translate the first 2Gig. (addr: 0x00 mask: 0x8F) Assuming your customer was wise enough to keep regions 3 and 4 below the 2Gig line, that is. Otherwise you'll have to get trickier. Valentin -- "An operating system without virtual memory Name: Valentin Pepelea is an operating system without virtue." Phone: (408) 985-1700 Usenet: mips!btr!valentin - Ancient Inca Proverb Internet: valentin@btr.com