Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!dali.cs.montana.edu!caen!sdd.hp.com!hplabs!hpl-opus!hpcc05!hpldsla!tonya
From: tonya@hpldsla.sid.hp.com (Tony Arnerich)
Newsgroups: sci.electronics
Subject: Re: flip/flops
Message-ID: <1990024@hpldsla.sid.hp.com>
Date: 21 May 91 20:28:28 GMT
References: <1943@ole.UUCP>
Organization: HP Scientific Instruments Division - Palo Alto, CA
Lines: 30


  >I have an interesting problem:

  >I want a logic equivalent of a flip/flop which can be configurable
  >with a mode switch. The inputs allowed are: D and Dbar, clk and mode.

  >When mode = 1; It should act as an edge triggered flip-flop (JK)
		 >and write on the rising edge of the clock.
  >When mode = 0; It should act as a level sensitive latch, and write
		 >on the logic high of the clock.

  >Minimum no. of logic gates (area) is critical as is no. of logic levels
  >(speed). Another restraint is to use inverters and nor gates only.

  >If you have had this problem before, or have a solution to this
  >problem, please mail me.

  >Thanks,
  >Shailendra
  >ssave@caen.engin.umich.edu

I have a better solution than my previous posting (which upon further
thought may be more difficult than I thought at first!).

Use the mode input to steer the pulses to either the CLK (toggle operation)
or change the state of the Set or Reset inputs of a normal JK flipflop. This
will work with one XOR gate if you only want one of Set or Reset functions.
Add a couple of logic gates for full D-type flip flop operation.

tonya@sid.hp.com