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Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!zephyr.ens.tek.com!tekgen!sail!arnief
From: arnief@sail.LABS.TEK.COM (Arnie Frisch)
Newsgroups: comp.lsi.cad,comp.lsi,sci.electronics
Subject: Re: 3.3V v/s 5V
Keywords: Vdd. 3.3v
Message-ID: <9577@sail.LABS.TEK.COM>
Date: 24 May 91 21:08:28 GMT
References: <1956@ole.UUCP>
Reply-To: arnief@sail.LABS.TEK.COM (Arnie Frisch)
Followup-To: comp.lsi.cad
Organization: Tektronix, Inc., Beaverton,  OR.
Lines: 23

In article <1956@ole.UUCP> ssave@ole.UUCP (Shailendra Save) writes:
>
>  In this week's Electronic Engineering Times (May 20th issue)
>  there is an article about AT&T developing a 3.3V cell library.
>  On pp 16, (bottom 2nd column) they claim:
>
>  The basic 2 input NAND-gate power rating is 6.1uW/MHz at 5V
>  dropping to 1.1uW/MHz at 3.3V
>
>  I am missing something here. If it is a CV^2 relationship,
>  it should be approx. 2.5 and not 1.1
>
>					Shailendra

The way these things work is that the charging current available is a
function of the difference between the power supply voltage and the
enhacement threshold voltage of the fets.  As you reduce the power
supply voltage, the circuit gets slower (and ultimately stops working)
at the same time the uW/Mhz get smaller, ultimately going to zero when
the fets no longer are turned on at all.

Arnold Frisch
Tektronix Laboratories