Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!wuarchive!uunet!mcsun!ukc!cam-cl!news
From: cet1@cl.cam.ac.uk (C.E. Thompson)
Newsgroups: comp.arch
Subject: Re: IEEE floating point
Message-ID: <1991May27.114846.2082@cl.cam.ac.uk>
Date: 27 May 91 11:48:46 GMT
References: <9105250030.AA08036@ucbvax.Berkeley.EDU> <1991May25.222551.16365@zoo.toronto.edu> <12805@mentor.cc.purdue.edu>
Reply-To: cet1@cl.cam.ac.uk (C.E. Thompson)
Organization: U of Cambridge Comp Lab, UK
Lines: 17

In article <12805@mentor.cc.purdue.edu> hrubin@pop.stat.purdue.edu (Herman Rubin) writes:
>
>The IBM hex FP is not that much worse than any other FP with 32-bit words.
>
>Some of the IEEE implementations make the 32-bit FP operations actually 
>more expensive than the longer ones, ...

This isn't unknown in implementations of IBM/360 FP either. On the 370/165,
for example, all SP adds and subtracts took one (80ns) cycle longer than the
corresponding DP ones. (In fact, the extra cycle was the first one, which
converted the operands to DP, and set a bit to cause the subsequent
register write to transfer only the first 32 bits of the result.) Multiply
and divide were faster in SP than DP, though.

Chris Thompson
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