Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!apple!motcsd!udc!aduane
From: aduane@urbana.mcd.mot.com (Andrew Duane)
Newsgroups: comp.arch
Subject: Re: VISC - A way to speed up moto cisc mpu's?
Message-ID: <2579@urbana.mcd.mot.com>
Date: 28 May 91 17:31:04 GMT
References: <1991May23.210000.8152@kithrup.COM> <2842@lee.SEAS.UCLA.EDU> <21621@brahms.udel.edu>
Sender: netnews@urbana.mcd.mot.com
Organization: Motorola Microcomputer Division, Urbana [IL] Design Center
Lines: 30

In article <21621@brahms.udel.edu> gdtltr@brahms.udel.edu (gdtltr@limbo.org (The Befuddled One)) writes:
>In article <13445@dog.ee.lbl.gov> torek@elf.ee.lbl.gov (Chris Torek) writes:
>=>Why not just build a multiprocessor system with completely different
>=>processors?  I.e., ship a system that contains, say, one 68040 and one
>=>or more 88x00s.  There is no particular reason that the O/S cannot run
>=>the proper binary on the proper CPU automatically.
>
>   There was a paper on something like this in Operating Systems Review
>about a year ago. The system was called AAMP (I think) and was written
>by someone from Sequent.

Perhaps this is the XA/MP architecture from Intel? I worked on some
whiteboard-type research to make a project proposal based on this
architecture last year. It was a combination of the 80x86 (where
'x' probably == 4), and the i860. Our instance of this would have
run Mach or somehting like it.

We looked at several problems with a heterogeneous architecture,
and (as long as byte order was the same between CPUs), the actual
selection of a processor to run a thread on was pretty simple.
We even figured out how to induce the compiler to emit both flavors
of object code, and let the exec facility select the right one.


Andrew L. Duane (JOT-7)  w:(408)366-4935
Motorola Microcomputer Design Center	 decvax!cg-atla!samsung!duane
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Only my cat shares my opinions, and she's too heavy to care.