Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!wuarchive!uunet!mcsun!corton!irisa!irisa.fr!wagner
From: wagner@irisa.fr (Charles Wagner)
Newsgroups: comp.lsi
Subject: self-timed circuit
Message-ID: <1991May27.160356.9584@irisa.fr>
Date: 27 May 91 16:03:56 GMT
Sender: news@irisa.fr
Reply-To: wagner@irisa.fr (Charles Wagner)
Organization: Irisa, Rennes(FR)
Lines: 8

A 6-transistor RAM cell with split word lines can perform either two reads or one write.
Time multiplexing a register array based on this cell with a two phase clocking method
needs an extra phase ( recover phase ) generated by using a self-timed circuit.
A row of dummy cells, hardwired to always contain a zero, is used to detect when 
a write has completed.
I am looking for the design of such a self-timed circuit.
If you can be of any help, please reply via email.
Thanks.