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From: swarren@convex.com (Steve Warren)
Newsgroups: comp.sys.amiga.advocacy
Subject: Re: Blitter vs. 040 (was: Computer Architecture question
Message-ID: <1991May28.152245.3656@convex.com>
Date: 28 May 91 15:22:45 GMT
References: <4987@orbit.cts.com> <1991May24.174930.20090@convex.com> <1248@cbmger.UUCP>
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In article <1248@cbmger.UUCP> peterk@cbmger.UUCP (Peter Kittel GERMANY) writes:
>In article <1991May24.174930.20090@convex.com> swarren@convex.com (Steve Warren) writes:
                                    [...]
>>yes? If all coprocessor control registers were implemented in zero-wait-state
>>static rams with non-blocking dual ports, that would allow a fast procesor to
>>program all the co-processors on the chip bus at full speed without even
>>slowing down.

>But you forget one *very important* Amiga feature: the Copper. This chip
>only can do its work on the chip bus, and it was created to change those
>registers on well defined moments via the chip bus. And it does a
>tremendous job. Unlike the blitter, no-one until now said that it would
>even be possible to emulate the copper through the CPU. So there's no
>way, the registers have to remain on the chip bus.

Hello, Peter.

Notice that I did not say to take all the registers off of the chip bus.  I
just said to implement them with a non-blocking dual port.  The port that is
not connected to the main processor of course must remain on the chip bus;
that is the whole reason why you need two ports.  There are ways to deal with
issues like timing without forcing the main processor to synchronize with the
chip bus.  Shadow ram could be employed.  The transfer from the shadow to the
real registers would be controlled by an arbitrator that knows the timing
rules for when the registers can change.  This can be made transparent to the
main processor.

A non-blocking multi-port memory design can often present issues like this
that would need to be resolved.  So never say, "there's no way," because it is
just a matter of expense versus payoff.  Sometimes the way to do it proves too
expensive when compared to the payoff.  In this example the assumption is that
the main processor looses a lot of time synchronizing with the chip bus and
waiting for cycles, strictly for the purpose of updating control registers.
If that is not true then there would not be much point in a scheme that only
speeds up accesses to the registers (and not to chip memory proper).

Regards,
--
            _.
--Steve   ._||__
  Warren   v\ *|
             V