Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!think.com!zaphod.mps.ohio-state.edu!unix.cis.pitt.edu!dsinc!bagate!cbmvax!daveh
From: daveh@cbmvax.commodore.com (Dave Haynie)
Newsgroups: comp.sys.amiga.graphics
Subject: Re: Idea for a graphics board
Keywords: 24 bit
Message-ID: <22035@cbmvax.commodore.com>
Date: 30 May 91 06:11:29 GMT
References: <1991May28.191019.13406@nntp-server.caltech.edu> <479@regina.uregina.ca> <1991May29.212315.27847@nntp-server.caltech.edu>
Reply-To: daveh@cbmvax.commodore.com (Dave Haynie)
Organization: Commodore, West Chester, PA
Lines: 33

In article <1991May29.212315.27847@nntp-server.caltech.edu> nygardm@nntp-server.caltech.edu (Michael T. Nygard) writes:
>I've been looking at some numbers on the board.  Here's what I came up with.

>Without using a CLUT (yuk.), assuming 80ns RAM, 1024x1024x24 resolution.

>1/(1024*1024*24*60) = .66227 ns/bit.
>(80 ns/cycle) / (.66227 ns/bit) = 120.8 bits/cycle

>That means a bus _at least_ 128 bits wide.  A 128 bit bus results in 5% of
>the memory cycles availible for the processor.

Uh, not to burst your bubble or anything, but the 80ns in an 80ns RAM chip
is the Row Access Time, not the cycle time.  The cycle time is usually 
around 150-160ns.  Of course, with page or static column mode DRAM, an 80ns
part may do an on-page cycle in around 50ns.

>Unless I go to video RAM, things could get unreasonable very fast.
>I know little about video RAM, could someone fill me in?

VRAM is likely what ya want on a board like that.  A VRAM has two ports, the
normal RAS/CAS random access port, and a serial shift register port.  You can
run a wacky cycle that, rather than pull a page or static mode trick, will
download a whole row into the shift register.  You can now proceed to shift
that data out quickly, while at the same time using the random access port for
CPU/GPU/whatever things.

>Mike Nygard


-- 
Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests"
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