Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!wuarchive!uunet!cbmvax!daveh From: daveh@cbmvax.commodore.com (Dave Haynie) Newsgroups: comp.sys.amiga.hardware Subject: Re: Breaking through the chip-bus barrier? Message-ID: <21982@cbmvax.commodore.com> Date: 28 May 91 20:24:07 GMT References: <1991May21.081806.2668@kberg.se> <1991May23.045536.1208@uniwa.uwa.oz> <1991May23.121032.31010@kuhub.cc.ukans.edu> Reply-To: daveh@cbmvax.commodore.com (Dave Haynie) Organization: Commodore, West Chester, PA Lines: 40 In article <1991May23.121032.31010@kuhub.cc.ukans.edu> markv@kuhub.cc.ukans.edu writes: >In article <1991May23.045536.1208@uniwa.uwa.oz>, andreww@uniwa.uwa.oz (Andrew John Williams) writes: >> svante@kberg.se (Svante Gellerstam) writes: >>>I would like to say that the highest hurdle to come over is the >>>bitplane concept. >> Why bother? Bitplanes generally gives higher video bandwidth (just look >> at Nat Semi's graphics chipset) and more importantly more processor - >> memory bandwidth (If its done right - the processor sees 1 bit/pixel and >> the hardware sorts out the rest) >I disagree to some extent. The relative merits of "chunky pixel" >versus bitplanes depends on the kind of work being done. >If you do some simple profiling and best/worse/average case scenarios, >you'll see that the more bitplanes you have (ie: 12,18,24 bit systems), >the worse bitplanes are versus chunky pixels. Again, it depends on the job and the hardware. In the aforementioned NS RGP8500 architecture, you have a separate blitter subsystem per bitplane. So the time it takes to draw a pixel, do a blit, draw a line, etc. is independent of the number of bitplanes; 10, 24, 100, it doesn't matter. Certainly, a few operations in this architecture, namely single pixel modification, are more expensive than an evenly packed pixel system. For example, an simple pixel write operation in a packed pixel system could be done with a single write, assuming the pixel depth is less than or equal to the size of the machine word. Doing the same write operation requires a read modify write cycle for the bitplane machine, one per bitplane. If these are all done in parallel, that's only twice as long as for the packed pixel machine. Logical operations on each system still require a read modify write cycle. This isn't, in any case, what's currently being done in the Amiga system. But a bitplane architecture does lend itself to obvious parallelism, while a packed pixel architecture does not. -- Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy "That's me in the corner, that's me in the spotlight" -R.E.M.