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From: gary@chpc.utexas.edu (Gary Smith)
Newsgroups: comp.sys.hp,comp.arch,comp.sys.apollo
Subject: Re: New 110 MIPS HP Snake at under $10,000.
Message-ID: <1991May28.191746.11508@chpc.utexas.edu>
Date: 28 May 91 19:17:46 GMT
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Reply-To: gary@chpc.utexas.edu (Gary Smith)
Organization: The University of Texas System CHPC
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I'm interested in the sustainable memory bandpass between the D-cache
and main memory on the Snake series.  Anyone know what it is?  Can it
sustain two 64-bit operands each clock?  If not, we have one more CPU
that can sit and wait for memory, right?
-- 
---Gary

Randolph Gary Smith                       Internet: gary@chpc.utexas.edu
Systems Group                             Phonenet: (512) 471-2411
Center for High Performance Computing     Snailnet: 10100 Burnet Road
The University of Texas System                      Austin, Texas 78758-4497